Memory devices are widely used in processing systems and consumer products. One type of memory device is a dynamic random access memory. Various kinds of DRAMs are commonly used. Typical examples are the synchronous DRAM (SDRAM) in which data is stored or retrieved in synchronism with a system clock and a double-data-rate SDRAM (DDR-SDRAM) which makes it possible to use both edges of a clock pulse as triggers for data access. In addition to the above described DRAMs, a RAMBUS DRAM (RDRAM) (under specifications of Ranibus Inc.) in which data transfer is enabled at a high speed with a protocol-based command, and the like have also been developed.
Three prominent trends in memory design and manufacturing have been the reduction in component size, reduced operating power levels and the increase in operating speed. These three trends are interrelated and often adversely affect each other. For example, component size reductions are necessary to achieve desired memory storage density without significant increases in die size. The reduction in component size can increase communication line resistances, which result in slower operating speeds and increased power consumption.
All memory devices use an addressing scheme to access memory cells, or locations. Specifically, many memory devices have memory cell arrays that are arranged in multiple banks of rows and columns. External address input connections are used to provide the bank, row and column addresses. These addresses are usually buffered and routed to different locations of the memory device.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device address management system that allows for reduced power consumption.